Greeting - EIDEC
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Greeting

EIDEC was founded in 2011, as a Japan-based international consortium to develop EUV lithography infrastructure technologies on blanks and patterned masks and resist materials for the half-pitch 11nm node and beyond.

In 2013, we started to develop Directed Self Assembly (DSA) technology to realize sub-10nm technology with a combination of EUV lithography technologies. In March 2016, we successfully completed all of our development programs.

The results we have secured so far could not have been achieved without global collaboration among leading companies from the semiconductor device, equipment, resist material and mask/blank business fields, and support from Japanese universities.

We are also pleased to say that we have won strong support from Japan's Ministry of Economy, Trade and Industry (METI), the New Energy and Industrial Technology Development Organization (NEDO) and the National Institute of Advanced Industrial Science and Technology (AIST).

We continue to pursue next generation device development as a private consortium, and we therefore decided to change the company’s name to “Evolving Nano-process Infrastructure Development Center, Inc.”, as a means to express our aim of developing nano-process platform technologies. The company’s abbreviation remains the same: “EIDEC”.

In June 2016, EIDEC‘s proposals were adopted as a part of a new national project in Japan. We are responsible for “Nano Defect Management (NDM).”

Alongside the national project, we will also promote private projects. They will depend on continued understanding and cooperation from all concerned parties. We sincerely appreciate your continuing strong support.

Hidemi Ishiuchi, President
Evolving Nano-process Infrastructure Development Center, Inc.